3 views
| Picture | Part Number | Manufacturer | Stock | Action |
|---|---|---|---|---|
 | ADS1115IDGSR | Texas Instruments | 9,180 | |
| ADS1015IDGSR | Texas Instruments | 4,550 | |
 | ADS112C04IPWR | Texas Instruments | 6,680 |
No. A direct 6.144 V input exceeds the PGA input limits of a 3.3 V board. The ±6.144 V setting scales the conversion code; at a 3.3 V supply, the recommended pin range remains 0 to 3.3 V. Use an input circuit that keeps the pin in range during normal operation and protects it during faults and power sequencing.
No. One conversion core serves the selected channel or pair. Effective ADS1115 channel throughput in an evenly divided four-channel scan has a nominal ceiling of 215 SPS per channel before I²C transfers and any settling or software delays. In single-shot mode, allow for wake-up time and wait for each result before reassigning it to a channel.
Yes. In differential mode, the converter subtracts AINN from AINP. When planning single-ended and differential ADC measurements, check the voltage on each pin separately. If AINP is at 0.9 V and AINN is at 1.1 V, the result is −0.2 V. With a suitable PGA setting and a 3.3 V supply, both pin voltages and the differential result are valid.
By Beebee Chiang
ADS1115IDGSR is a Texas Instruments 16-bit, 860 SPS I²C delta-sigma ADC in a 10-pin VSSOP whose PGA scales code span without extending VDD rails. Selecting ±6.144 V does not make a 6 V signal safe on a 3.3 V VDD supply, because PGA input limits still restrict each pin to GND through VDD. Because four inputs share one core, budget ADS1115 channel throughput across mux writes and I²C reads.
The TI ADS111x datasheet, §§6.1, 6.3 and 7.3.3, gives three limits that serve different purposes. The recommended input range is GND to VDD at each analog pin. The absolute maximum range extends from −0.3 V to VDD + 0.3 V; these are stress limits and do not extend the measurement range. The programmable gain amplifier (PGA) sets a full-scale range for the voltage difference between the inputs chosen by the MUX.
No. A smaller range gives a finer code step, but the converter’s effective input impedance also changes with gain. Check loading, settling, noise and overload headroom with the intended source and protection components. Buffering can improve the result when the sensor cannot comfortably drive the ADC input.
Use the full TI part number and confirm the DGS 10-pin VSSOP package, reel requirement, quantity and delivery date. If a substitute is requested, include the supply voltage, input modes, per-pin voltage envelope and required update rate for every channel so that engineering can compare actual fit.
These PGA input limits matter when either sensor lead can move with respect to board ground. For example, consider three differential measurements at VDD = 3.3 V. The voltages below are illustrative and assume a common ground reference.
Table 1: Input checks at 3.3 V | Source: TI ADS111x datasheet, §§6.1, 6.3, 7.3.3 | Compiled by: YG GROUP
| AINP / AINN | Selected PGA range | Expected result |
|---|---|---|
| 1.80 V / 2.00 V | ±0.256 V | Both pins and the −0.20 V difference are in range. |
| 2.90 V / 0.90 V | ±1.024 V | Both pins are in range, but the +2.00 V difference clips the conversion code. |
| 3.80 V / 3.70 V | ±0.256 V | The +0.10 V difference is within the code span; both pins exceed the 3.6 V absolute maximum for this supply. |
The second and third cases call for different fixes. In the second, selecting a wider range recovers the signal at a coarser code step. In the third, changing the PGA cannot correct the voltage at either pin. Consider attenuation, level shifting or a different analog front end, including protection for the case where the sensor stays powered after the ADC supply turns off.
Figure 1: Illustrative 3.3 V ADS1115 input checks separate the voltage at each pin from the selected differential PGA span. | Source: TI ADS111x datasheet, §§6.1, 6.3 and 7.3.3 | Chart: YG GROUP
For a 16-bit bipolar code, the nominal step equals the full span divided by 65,536. At ±4.096 V that is 125 µV per count; at ±0.256 V it is 7.8125 µV per count. Neither number is an accuracy specification. Check noise, offset and gain error, and account for what the source sees when driving the ADC. TI describes a switched-capacitor input and lists typical differential input impedance that falls from 4.9 MΩ at ±2.048 V to 710 kΩ at ±0.256 V. If your sensor or protection network has appreciable source resistance, check the loading error before counting on a finer code step. A buffer or a different resistor network can be more useful than another gain setting. See the electrical characteristics and analog input discussion.
A single-ended channel measures one selected input relative to ground. A differential selection measures the difference between a supported pair. For example, the MUX supports AIN0–AIN1 and AIN2–AIN3; a negative result means the first pin is lower than the second, not that a pin can go below ground. For single-ended and differential ADC inputs, specify the MUX settings and channel pairs the firmware needs.
To estimate ADS1115 channel throughput, start with 1/860 s, about 1.16 ms per conversion at the nominal maximum data rate. Dividing 860 by four yields an ideal 215 SPS per channel before any overhead. For a single-shot scan, the device takes approximately 25 µs to wake before a conversion. At 400 kHz I²C, a configuration write plus a pointer write and two-byte result read use 81 clock pulses including ACK/NACK bits, about 203 µs. If those transfers are serialized with conversion and wake time, the illustrative budget is about 1.39 ms per result, or 180 SPS per channel in an equal four-channel scan. Bus conditions, readiness polling, scheduling, the oscillator’s data-rate tolerance and board settling can change that figure. It is a planning example, not a measured or specified rate.
Pair each sample with the MUX setting that produced it. In continuous mode, a conversion already in progress can complete with the previous configuration after the next MUX setting is written. In single-shot mode, wait for the new conversion to finish before reading and tagging the result. The conversion mode and Config register descriptions explain when new settings take effect and how to check readiness.
Selecting the right alternative requires deciding whether the application can trade resolution for speed or needs a different sensor front end. Keep package, firmware and source impedance on the comparison list even when two TI orderables have similar names.
Table 2: TI ADC candidates to review | Source: ADS1015IDGSR, ADS112C04IPWR | Compiled by: YG GROUP
| Candidate | Reason to evaluate it | What to verify before changing the BOM |
|---|---|---|
| ADS1015IDGSR | 12-bit ADC with data rates up to 3.3 kSPS and a 10-pin VSSOP package | Code scale, rate programming, effective resolution and sensor error budget |
| ADS112C04IPWR | 16-bit I²C ADC up to 2 kSPS with excitation current sources for sensor designs | 16-pin TSSOP layout, input circuit and firmware changes |
For the original design, TI’s exact ADS1115IDGSR page identifies the DGS 10-pin VSSOP orderable with a large reel. If you are quoting this ADC alongside other Texas Instruments parts, share the BOM lines, quantities and need-by date in a YG GROUP RFQ. For the ADC, include VDD, the minimum and maximum voltage on each sensor lead, the source resistance or input filter, the channel pairs, and the required update rate per channel. Those details distinguish a quote for the original part from an alternative that needs engineering review. For related ADC input-stage and I²C sensing checks, see our guides on ADC driver and RC input settling and 10-pin VSSOP I²C monitor selection.