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AD7685ARMZRL7: Driver Settling for Test Instruments

The C-grade MSOP part is a comparison candidate when the linearity requirement is tighter. The A-grade LFCSP option changes the package and footprint while retaining the cited A-grade limits. Neither comparison removes the need to review the complete application and controlled BOM.

Start the design budget with those exact limits, then add the external signal-chain errors. A driver that settles to a fraction of an LSB is useful because it avoids adding a large dynamic error. It does not transform A-grade converter linearity into the C-grade guarantee.

What the driver sees during acquisition

The AD7685 samples the difference between IN+ and IN− when CNV rises. The allowed signal span is 0 V to VREF, with IN− acting as a ground-sense input rather than an unrestricted differential signal input. The specification table limits IN− to approximately ground, −0.1 V to +0.1 V under its stated conditions. A bipolar instrument input therefore needs a suitable external scaling and offset circuit; it cannot simply be connected across the two ADC inputs.

During acquisition, the internal sampling network connects to the signal source. The datasheet's simplified model includes a typical 3 kΩ internal resistance and a typical 30 pF sampling capacitance, together with pin capacitance. During conversion, the sampling switch opens. The input is therefore a switched load, not a static resistor or an ordinary high-impedance voltmeter input. AD7685 datasheet, pp. 8 and 13–15

That distinction matters most after an external multiplexer changes channel. The amplifier may have to recover from a large step, charge an external filter capacitor, and then replenish the ADC sampling network before the next CNV edge. Source resistance, multiplexer resistance, amplifier output impedance, filter values, and parasitic capacitance all participate.

The datasheet's typical THD-versus-source-resistance plot illustrates another consequence: a source that looks adequate for a slowly changing DC measurement may give worse distortion for a higher-frequency signal. Use the actual signal bandwidth and error requirement when deciding whether direct drive is acceptable.

Establish the acquisition window before choosing an amplifier

The maximum sample rate depends on VDD. At VDD from 4.5 V to 5.5 V, the timing table gives a minimum 4 µs cycle, a maximum 2.2 µs conversion time, and a minimum 1.8 µs acquisition time. At the lower supply range, the cycle is 5 µs minimum and conversion time is 3.2 µs maximum, retaining the 1.8 µs minimum acquisition interval. Thus a 3.3 V design should use the 200 kSPS limit, not automatically copy the 250 kSPS family headline. AD7685 datasheet, pp. 3 and 5–6

For a 5 V, 250 kSPS example, the worst-case converter timing leaves:

4.0 µs cycle − 2.2 µs maximum conversion = 1.8 µs acquisition

That interval is a timing requirement, not a promise that every external amplifier will settle within it. If an external channel changes late in the cycle, its available settling time can be shorter. If it changes during conversion, the driver and external filter can begin moving earlier, but the internal sampling capacitor reconnects only when acquisition begins. Check both events.

Draw the actual sequence around CNV: channel selection, multiplexer propagation, amplifier slew and recovery, ADC acquisition, conversion, and data readback. The sample represents the input at the CNV edge, not at the end of the later SPI transaction. A correct serial word can therefore contain a settling error established before conversion started.

A first-order calculation gives a screening target

For an ideal single-pole response to a full-scale step, the remaining fractional error is exp(−t/τ). If the design allocates half of one 16-bit LSB to settling, the required fractional error is 1/131072, approximately 7.63 ppm. The corresponding settling interval is approximately:

t = ln(131072) × τ ≈ 11.78 × τ

Using a 1.8 µs interval gives an illustrative time-constant target of about 153 ns or less. This is a deliberately chosen engineering allocation, not an ADC specification or proof of driver performance.

The datasheet's example input filter uses 33 Ω and 2.7 nF. Their simple product is 89.1 ns. Comparing that with the screening target is informative, but it does not qualify the circuit. The ADC adds a switched sampling network, while the real amplifier has finite bandwidth, output impedance, slew rate, and potentially a long settling tail. Capacitive-load stability and multiplexed step size also matter.

An amplifier specified to settle to 0.1% or 0.01% has not thereby been specified to settle to 7.63 ppm. The AD7685 driver guidance explicitly calls out the need to verify settling at the required converter resolution. Use small-error settling data or an appropriate bench test rather than extrapolating a faster, looser specification.

Balance filter noise reduction against settling and stability

A series resistor and shunt capacitor can reduce wideband noise and isolate the amplifier from the sampling transient. Increasing their time constant also slows recovery after a channel change. Making the capacitor larger without checking the amplifier can introduce ringing or instability; making the resistor larger can worsen source-impedance-related dynamic error.

Choose the filter as part of the complete input network. Establish the desired signal bandwidth and attenuation, then check the amplifier's stable load range and the acquisition error at the largest relevant step. Include multiplexer on-resistance and its variation if a multiplexer precedes the driver or filter.

The datasheet lists several candidate driver families, including ADA4841, AD8605, and AD8021, for different noise, supply, power, and frequency objectives. That list is a starting point. It is not a statement that every listed amplifier will meet any instrument's input span, rail voltage, filter load, or multiplexing rate. A final amplifier choice requires its own full specifications and circuit validation. AD7685 datasheet, p. 16

Keep the noise calculation tied to noise gain and bandwidth. The amplifier's input voltage-noise density alone does not establish output-referred integrated noise. Feedback resistors, source impedance, current noise where relevant, and the filter response can affect the result. Treat noise and settling as two simultaneous requirements; slowing the filter until a quiet DC histogram looks good can conceal a channel-switching problem.

Give the reference its own recovery check

REF is also a dynamic load. The average reference-load current listed in the specification does not describe every transient current needed during charge redistribution. The reference source, any buffer, the local capacitor, and the interconnect must hold the reference adequately stable throughout conversion.

For a very low-impedance reference source or buffer, the datasheet discusses a 10 µF X5R ceramic capacitor. For its unbuffered ADR43x example, it discusses 22 µF. These recommendations depend on the source circuit; they are not interchangeable values independent of buffer behavior. The local capacitance under DC bias and the source's ability to drive that load both deserve review. AD7685 datasheet, pp. 16 and 24

Place the reference decoupling capacitor close to REF and GND with a short, low-inductance loop. Decouple VDD and VIO locally as well. Keep clock and conversion-control routing away from the analog input and reference paths. A reference error synchronous with conversion may not appear in a slow multimeter reading.

When investigating an error that changes with sample rate, test the input driver and reference separately. A longer cycle gives both networks more recovery time, so improved results at a slower rate do not identify the input driver as the cause by themselves.

Verify the host timing without confusing it with analog settling

The ADC performs conversion with its internal clock; SCK is used for serial readout. CS modes and chain modes impose different CNV, SDI, and SCK timing relationships. Select the interface deliberately and implement the corresponding timing diagram.

Without a BUSY indication, wait for the maximum conversion time applicable to the supply. With BUSY enabled, respect the mode's signal levels and readout sequence. Include the host's setup and hold requirements, SDO delay, trace loading, and any isolation delay. Daisy chaining increases the number of bits that must be read within the chosen cycle.

VIO supports low-voltage logic interfacing, but the datasheet distinguishes the 1.8 V operating range from the 2.3 V lower bound used for several specified-performance and timing tables. Do not assume every published timing limit is guaranteed at 1.8 V simply because the interface can operate there. AD7685 datasheet, pp. 4–6 and 17–23

A bench sequence that separates likely error sources

The following is a proposed validation method, not a report of tests performed on this part:

1. Establish static behavior. Apply a stable input comfortably inside the valid range. Collect raw codes at several sample rates, preserving reference voltage, temperature, and supply conditions.
2. Exercise channel history. Alternate between low and high inputs within the valid span. Compare the first code after switching with later codes after the same channel has remained selected.
3. Sweep the available settling interval. Change the delay between channel selection and CNV while preserving the intended SPI behavior. Record where the result stops moving within the measurement uncertainty.
4. Check reference sensitivity. Observe REF with a suitable low-loading measurement arrangement and compare behavior for the different code histories and sample rates.
5. Test dynamic performance. Use an adequately clean signal source at the required frequencies and amplitudes. Separate fixture and generator limitations from converter behavior.
6. Repeat important corners. Include the specified operating temperature, supply variation, input span, channel combinations, and production component tolerances relevant to the instrument.

Preserve the conditions and uncertainty beside each result. If a first-sample error disappears with more settling time, that is useful diagnostic evidence, but it still requires investigation of the driver, multiplexer, reference, and timing together. Discarding the first sample may be a valid system choice only after its effect on throughput and measurement requirements is accepted.

Approve the entire acquisition path

A defensible AD7685ARMZRL7 design connects the exact A-grade guarantees to a measured acquisition budget. Allocate dynamic error before choosing the driver, validate the largest channel transitions, and check reference recovery and digital timing independently. The result is an instrument-level performance record rather than a collection of favorable component headline values.

By Kelsey Lee

References

• Analog Devices — AD7685 Rev. D datasheet. Rev. D, July 2014. Grade and package ordering, electrical and timing tables, driver/reference guidance, serial modes, and layout.
• Analog Devices — AD7685 product and exact model listings. Checked September 20, 2026, to corroborate the exact ordering model and manufacturer documentation.