MAX5882

The MAX5882 14-bit, 4.6Gsps digital-to-analog converter (DAC) is designed for direct RF synthesis of multicarrier quadrature amplitude modulation (QAM) signals in cable modem termination systems (CMTS) and edge QAM (EQAM) devices. The DAC features excellent spurious, noise, and adjacent-channel power (ACP) performance, and directly synthesizes multiple carriers in the 47MHz to 1003MHz cable downstream band, as defined by the Data-Over-Cable Service Interface Specification (DOCSIS®). The 4.6Gsps update rate allows digital generation of signals with more than 2GHz bandwidth.The device has four 14-bit, multiplexed, low-voltage differential signaling (LVDS) input ports that each operate at up to 1150Mwps in double data rate (DDR) or single data rate (SDR) mode. The inputs also accept differential high-speed transceiver logic (DHSTL) input levels. The device accepts a clock at 1/2 the DAC update rate, as conversion is triggered on both rising and falling clock edges. The input data rate on each port is 1/4 the DAC update rate or 1/2 of the clock rate. The device contains a delay-locked loop (DLL) that simplifies the interface to FPGA or ASIC devices. Using the DLL, the phase of the output clock (DATACLK) is adjusted to ensure that the input LVDS data bus has the proper timing relationship to the on-chip clock used to latch the data.The device is a current-steering DAC with an integrated 50Ω differential output termination to ensure optimum dynamic performance. Operating from 3.3V and 1.8V power supplies, the device consumes 2.3W at 4.6Gsps. The device is specified over the upper commercial temperature range (0°C to +85°C) and is offered in a 256 CSBGA lead(Pb)-free/RoHS-compliant package.