Veca Huang
| Picture | Part Number | Manufacturer | Stock | Action |
|---|---|---|---|---|
 | STM32F407VGT6 | STMicroelectronics | 9,660 | |
| STM32F407VET6 | STMicroelectronics | 3,860 |
At 12-bit resolution and SMP = 15 on every rank, each conversion takes 15 + 12 = 27 ADC cycles. Four ranks take 108 cycles, so the conversion sequence is 108 / 21 MHz = 5.143 µs. A conservative external-trigger latency budget of 2/ADCCLK + 1/PCLK2 adds 0.107 µs at PCLK2 = 84 MHz. DMA service and other conversion groups require separate consideration.
No. Trigger overlap and conversion-data loss are different conditions. OVR reports lost data when overrun detection is enabled, which includes DMA = 1 or EOCS = 1. Do not infer OVR or a fixed channel rotation from an overlapping timer event. Schedule complete sequences and inspect the ADC/DMA status when diagnosing missing frames.
Gate further timer requests and inspect the active frame. RM0090 §13.8.1 requires reinitializing DMA, including destination address and NDTR, clearing ADC_SR.OVR, and restarting conversion. Restore the intended ADC/DMA state before re-enabling periodic triggers. An isolated flag clear does not by itself establish that the next memory position is rank 1.
By Veca Huang | YG GROUP
STM32F407VGT6 timer-driven ADC sampling works when each regular sequence fits between accepted triggers and every conversion result reaches memory before it is lost. With PCLK2 at 84 MHz, a divide-by-four ADC clock and four 12-bit ranks using 15 sampling cycles each, the scan requires 108 ADC cycles, or 5.143 µs. Trigger latency and DMA service need separate allowances; OVR identifies lost conversion data rather than a generic timer-overlap event.
STM32F407VGT6 provides three 12-bit ADCs, but a single ADC still converts the ranks in its regular group sequentially. A four-channel scan is four ordered conversions, not four simultaneous samples. Configure the desired channel number at each sequence rank, set the sequence length to four, and use scan mode. For one complete scan per timer event, keep continuous conversion disabled and avoid discontinuous mode, which deliberately divides a sequence across trigger events.
The ADC clock is derived from PCLK2 through a divide-by-2, -4, -6 or -8 prescaler. At a 168 MHz core configuration with PCLK2 = 84 MHz, dividing by four gives ADCCLK = 21 MHz. Dividing by two would give 42 MHz, beyond the datasheet’s 36 MHz ADC limit at VDDA = 2.4–3.6 V. At VDDA = 1.8–2.4 V the listed maximum is 18 MHz, so even the 21 MHz example does not apply at that lower supply range. A supported clock and supply condition must precede any sampling-rate calculation.
For a concrete regular trigger, RM0090 selects TIM2_TRGO with EXTSEL = 0b0110; EXTEN = 0b01 enables rising-edge detection. Configure the timer’s master output deliberately rather than assuming that enabling the timer establishes TRGO. This article’s budget assumes ADC1 independent operation, no injected conversion interrupting the scan, and an already stabilized ADC.
The 100-lead LQFP uses VSSA pin 20, VREF+ pin 21 and VDDA pin 22. PA0 / ADC input 0 is pin 23. This LQFP package has no exposed pad. The shared VDDA/VREF+ option shown in DS8626 Figure 52 uses 1 µF and 10 nF bypassing to VSSA; supply and connect all remaining power pins as required by the complete datasheet.
For a 12-bit result, the conversion time is the selected sampling interval plus 12 ADC cycles. Sum that time across every rank; use each channel’s actual sampling setting when the values differ. The following example uses 15 sampling cycles on all four ranks.
Table 1. Calculated four-rank ADC sampling budget | Source: manufacturer documents in References; assumptions and operating conditions are stated in the table or adjacent text. Compiled / calculated by: YG GROUP.
| Quantity | Calculation | Result / condition |
|---|---|---|
| ADC clock | 84 MHz / 4 | 21 MHz, VDDA = 3.3 V example |
| One rank | (15 + 12) / 21 MHz | 1.286 µs |
| Four-rank scan | 4 × 27 / 21 MHz | 5.143 µs |
| Conservative external-trigger latency allowance | 2 / 21 MHz + 1 / 84 MHz | 0.107 µs |
| Trigger to last conversion result | 5.143 + 0.107 µs | 5.250 µs, excluding DMA service |
| Illustrative trigger period | 10 µs | 100,000 complete scans/s; 100 ksample/s per rank |
A 10 µs period leaves 4.75 µs after this conservative trigger-to-last-result budget. It is a design example, not a guaranteed safe operating point or a manufacturer-required margin factor. The four results total 400 ksample/s, while each channel is sampled once per accepted scan. DMA arbitration, memory traffic, firmware processing and any injected conversions still need validation.
Figure 1. Calculated timing for PCLK2 = 84 MHz, ADCCLK = 21 MHz, 12-bit resolution and four ranks at SMP = 15. A conservative external-trigger latency allowance brings the trigger-to-last-result budget to 5.250 µs; DMA service is excluded. The lower flow shows data loss with DMA enabled, not an automatic consequence of trigger overlap. Sources: DS8626 Rev 12 Table 67 and RM0090 Rev 18 §§13.5, 13.8; calculation / diagram: YG GROUP.
An event at 4 µs falls inside this example’s current sequence. Avoid scheduling that overlap: the regular conversion engine is not an unlimited queue of scan requests. An overlapping event does not itself prove that OVR was set, that a new rank started, or that the DMA buffer shifted by one channel. Those conclusions require the ADC mode, status and captured memory history.
Regular conversions use one ADC data register. With DMA enabled, each completed rank requests a transfer from ADC_DR to the destination buffer. For right-aligned 12-bit results, a halfword buffer can hold one value per rank. Program the appropriate ADC DMA request mapping and transfer sizes for the selected ADC; do not copy a stream/channel assignment from another ADC instance.
Choose a buffer length that contains a whole number of four-rank frames. For example, 256 halfwords hold 64 frames. In a circular-buffer design, the 128-halfword half-transfer boundary also contains 32 complete frames, so the consumer can process a stable half without starting in the middle of a sequence. This arrangement helps software interpret the data; it does not remove the DMA bandwidth deadline.
RM0090’s DDS field controls whether requests continue beyond the configured final transfer. Periodic acquisition needs an ADC request policy that matches the DMA circular or double-buffer arrangement. Enabling only DMA without checking DDS, NDTR and buffer ownership can produce a one-shot acquisition or a stalled stream. Start the ADC and DMA in the intended state before admitting the first periodic trigger, and only process a buffer half after its completion event.
OVR is set when conversion data are lost with overrun detection enabled. DMA = 1 or EOCS = 1 enables that detection. A useful example is a rank completing while the preceding ADC_DR result has not been read: the memory service deadline was missed even if the next timer event is comfortably far away.
In DMA mode, RM0090 §13.8.1 describes stopped DMA requests after overrun and the need to reinitialize acquisition. Gate periodic triggers, inspect the affected frame, restore the DMA destination address and NDTR, clear OVR, and restart the ADC/DMA state before resuming the timer stream. The manual requires DMA reinitialization; merely clearing the status flag is insufficient evidence that the next transfer will represent rank 1 at buffer index zero.
Log ADC_SR and the DMA status when the failure occurs. Separate an ADC overrun from a DMA transfer error, a consumer that reads an unfinished half, or an incorrect sequence-length setting. An occasional missing scan and a repeatedly rotated channel interpretation are different symptoms. Do not repair either by silently relabeling the buffer until the trigger and frame history are understood.
Sampling time also serves an analog purpose. The external source must charge the ADC’s sampling capacitance through the source resistance and internal input resistance. DS8626 lists CADC as 4 pF typical and RADC with a 6 kΩ maximum; its source-impedance equation also depends on resolution, ADCCLK and sampling cycles. A universal table claiming that a particular sampling code always supports one fixed RAIN value hides those conditions.
Use the datasheet equation and the real source’s settling behavior when selecting SMP. A high-impedance divider or slow amplifier may need a longer sampling interval, which lengthens the total sequence and requires the timer budget to be recalculated. Validate the first conversion after a large channel-to-channel input step. A longer digital interval cannot compensate for an unstable reference or an input outside the allowed analog range.
Figure 2. Illustrative partial circuit for the 100-lead LQFP. RADC ≤ 6 kΩ and CADC = 4 pF typical belong to the simplified input model; Rsource is external. The shared-reference option uses 1 µF and 10 nF bypass capacitors between VDDA/VREF+ and VSSA. Other power pins and input protection are omitted. Source: DS8626 Rev 12 pin table and Figures 50–52.
For this exact 100-lead LQFP, VSSA is pin 20, VREF+ is pin 21 and VDDA is pin 22. PA0 / IN0 is pin 23. The package has no exposed pad. Figure 2 shows the datasheet’s shared VDDA/VREF+ option with 1 µF and 10 nF bypassing; a separate external reference is another documented option. These analog connections are only part of the full supply design. Connect the remaining supply pins, regulator capacitors and grounds using the complete package-specific guidance.
Bring up the system with distinct, stable voltages at each selected input. Check that each completed frame preserves rank order, then test channel transitions and the planned bus load. Record timer frequency, actual ADC prescaler, sampling settings, DMA boundaries and OVR status. These checks are proposed engineering validation steps; no bench measurements are claimed here.
Table 2. Same-family memory and package comparison | Source: manufacturer documents in References; assumptions and operating conditions are stated in the table or adjacent text. Compiled / calculated by: YG GROUP.
| Exact model | Verified memory / package difference | Relevance to this scan design |
|---|---|---|
| STM32F407VGT6 | 1 MB Flash, 192 KB listed SRAM, LQFP100 | Primary device used in the calculations |
| STM32F407VET6 | 512 KB Flash, same listed SRAM and LQFP100 family | Possible capacity alternative; the same ADC timing constraints remain |
The comparison follows DS8626. It does not establish that an existing binary, memory map or board configuration transfers without review. Select the memory density around the application’s needs, then verify acquisition timing on the chosen device. Changing the Flash suffix does not resolve a trigger period that is shorter than the configured scan or a DMA path that cannot preserve its results.