Jolin Zeng
Only A and B contain MPSSE engines. C and D support UART plus synchronous and asynchronous bit-bang, but no MPSSE. Route hardware synchronous-protocol requirements to A or B and configure the chosen mode in host software.
Yes. FT_000060 §4.5 permits synchronous and asynchronous bit-bang on all four channels. Synchronous bit-bang samples inputs before updating the corresponding output, so returned samples are one byte behind the transmitted output sequence. It is not an MPSSE engine.
No. It is the high-speed USB line rate. Useful throughput depends on USB overhead, shared traffic, command batching, the target protocol and host behavior. UART baud rate and MPSSE clock/data-rate limits are separate specifications.
For the 64-pin QFN, the package drawing gives 4.35 × 4.35 mm nominal, with 4.30–4.40 mm limits, and requires connection to system ground. These are package-pad dimensions. The 56-pin variant and the production PCB paste pattern have different requirements.
No. The datasheet states that channels reset to asynchronous UART mode and host software must reconfigure them. The external EEPROM stores USB descriptors and supported configuration options; it is not a persistent channel-mode assignment mechanism.
By Jolin Zeng | YG GROUP
The FT4232HQ provides four USB interfaces, but only channels A and B contain MPSSE engines for synchronous protocols. All four channels can use UART or synchronous/asynchronous bit-bang modes. A reliable interface plan separates those capabilities from USB line rate, EEPROM descriptors and the QFN64 power connections.
Four USB interfaces do not mean four MPSSE engines. The FT4232HQ gives a host four independently configurable channels, but channels A and B alone include the hardware engine used for JTAG, SPI and other synchronous protocols. If a board routes its only JTAG connector to channel C and expects MPSSE commands to work, software cannot add the missing engine after assembly.
The FTDI FT4232H datasheet, FT_000060 version 2.9, is the reference for this interface plan. FT4232HQ identifies the 64-pin QFN variant. Its pin numbers must not be borrowed from the smaller FT4232H-56Q package. The two variants support the same general functions, but their supply pins, signal numbers and mechanical dimensions differ.
Table 1. Available hardware functions by channel | Source: manufacturer documents in References; assumptions and operating conditions are stated in the table or adjacent text. Compiled / calculated by: YG GROUP.
| Channel | UART | Asynchronous bit-bang | Synchronous bit-bang | MPSSE |
|---|---|---|---|---|
| A | Yes | Yes | Yes | Yes |
| B | Yes | Yes | Yes | Yes |
| C | Yes | Yes | Yes | No |
| D | Yes | Yes | Yes | No |
This matrix follows §§3.1.4 and 4.5. A channel’s pins implement the selected mode; the same pins cannot simultaneously serve as a full UART and an MPSSE interface. C and D can provide GPIO through bit-bang modes, so they should not be described as UART-only. Bit-bang remains distinct from an MPSSE command processor: the host must arrange pin patterns and sampling according to that mode’s rules.
A useful example assigns A to an SPI peripheral, B to JTAG, C to a debug UART and D to slow GPIO. Two SPI targets can also share a suitable SPI engine with separately managed chip-select lines when their electrical and protocol requirements permit it. That does not create a third independent synchronous engine or guarantee concurrent timing across targets.
Figure 1. Illustrative allocation based on FT_000060 Tables 3.5–3.7 and §4.4. A/B each contain one MPSSE; C/D support UART and both bit-bang modes. SPI and JTAG examples are mutually selected channel configurations, not simultaneous modes on one channel. Source: manufacturer documents in References; calculation / diagram: YG GROUP.
For QFN64 channel A in MPSSE mode, pin 16 is TCK/SK, pin 17 TDI/DO, pin 18 TDO/DI and pin 19 TMS/CS. Channel B uses pins 26, 27, 28 and 29 for those roles. Clock and DO are outputs from the bridge; DI is an input to it. In a JTAG drawing, the target’s TDO must reach the bridge’s TDO/DI input. Labels taken from opposite ends of a cable without direction arrows can otherwise reverse the data path.
UART TXD is likewise an output from the bridge and RXD an input. These are logic-level signals. An RS232 or RS485 connector requires the appropriate external level-conversion or transceiver circuit; the FT4232HQ does not directly produce those cable-level voltages. For RS485, the datasheet describes a configurable TXDEN function. Check the selected EEPROM option and transceiver enables before assuming an arbitrary GPIO will provide the intended automatic timing.
The USB connection supports a 480 Mbit/s high-speed line rate. That value is not the application’s sustained payload rate, an individual UART baud rate or a per-channel guarantee. The datasheet specifies UART operation up to 12 Mbaud and MPSSE operation up to 30 Mbit/s with the stated engine timing. Protocol overhead, direction changes, host commands and target response can reduce useful throughput.
Each channel has its own 2 Kbyte transmit and receive buffers, while the channels share the USB connection. Independent buffers do not create four independent USB links. Batch appropriate MPSSE commands rather than requiring a host round trip for every clock edge, but measure the complete operation including commands, reads and target waits. A quoted transfer result needs a payload definition, target protocol, clock setting, host environment and error criterion.
In synchronous bit-bang mode, the input sample precedes the corresponding output update. The datasheet’s example begins at 0xFF, sends 0x55 then 0xAA, and receives 0xFF then 0x55. Another transmitted byte is needed to sample the last output state. This one-byte relationship matters when D is used to drive a control signal and observe its response. It is not a zero-latency feedback loop.
The core supply is nominally 1.8 V. The documented VCORE operating range is 1.62–1.98 V. VCCIO is nominally 3.3 V, with a 2.97–3.63 V range; the input cells' 5 V tolerance does not permit powering VCCIO from 5 V. USB PHY and PLL supplies have their own 3.0–3.6 V operating limits.
On QFN64, pin 50 VREGIN receives the regulator input, and pin 49 VREGOUT supplies the internal regulator’s 1.8 V output. The board must connect that output to VCORE pins 12, 37 and 64, with the specified 3.3 µF filtering. There is no internal connection that removes that routing requirement. All VCCIO pins—20, 31, 42 and 56—must be connected. Figure 2 shows only the supply subset needed to clarify these distinctions.
Figure 2. Illustrative partial power schematic from FT_000060 Tables 3.2 and Figure 8.1. VREGOUT feeds VCORE pins 12, 37 and 64 with a 3.3 µF filter capacitor. The QFN64 central pad is 4.35 × 4.35 mm nominal (4.30–4.40 mm), not a production land-pattern specification; other required pins and bypassing are omitted for clarity. Source: manufacturer documents in References; calculation / diagram: YG GROUP.
The 64-pin QFN body is 9 × 9 mm with 0.5 mm pitch. Its bottom central solder pad must connect to system ground. Do not use the 5.90 mm pad of the 56-pin variant or a timing-table number as a mechanical dimension. Use the correct package drawing and assembly recommendations for the production footprint, paste design and ground connection. The partial diagram does not omit the need for the other grounds, PHY/PLL supply treatment, crystal, reference resistor, reset handling and local bypassing.
An external 93C46, 93C56 or 93C66-type EEPROM, configured 16 bits wide and meeting the documented supply and clock requirements, can store USB descriptors and options such as drive strength or RS485 TXDEN selection. It does not permanently assign MPSSE mode to a channel. After reset, the four channels return to asynchronous UART mode and host software must configure the desired modes again.
Use the documented device serial number and interface identity when software selects a channel. This source does not establish a separate freely programmable USB product string for each channel, so no such promise is needed for the allocation plan. With no EEPROM or a blank EEPROM, the device uses its default descriptors and lacks a programmed serial number; deterministic device identification then needs particular care.
Table 2. Related package comparison | Source: manufacturer documents in References; assumptions and operating conditions are stated in the table or adjacent text. Compiled / calculated by: YG GROUP.
| Model | Verified interface resources | Mechanical boundary |
|---|---|---|
| FT4232HQ | Four channels; A/B MPSSE | 64-pin QFN, primary device |
| FT4232HL | Same family resources and 64-pin signal numbering | 64-pin LQFP; different footprint and assembly |
The datasheet lists this same-family option. Before approving the design, confirm channel identity after reset, set each intended mode, check target signal directions and test one protocol at a time. Then exercise simultaneous traffic, suspend/resume and reconnect. Check the supply network and ground pad against the exact QFN64 drawing. These tests establish the application’s working allocation; they do not turn a USB line-rate headline into a throughput guarantee.