Beebee Chiang
| Picture | Part Number | Manufacturer | Stock | Action |
|---|---|---|---|---|
 | AT24C02D-SSHM-T | Microchip | 1,340 | |
 | AT24C01D-SSHM-T | Microchip | 1,220 |
No. WP is sampled at STOP before the internal self-timed cycle begins. Once that STOP has initiated programming, changing WP does not alter or interrupt the cycle. Power-fail protection must prevent new writes and provide adequate power or a recoverable record scheme for accepted writes.
The AT24C02D acknowledges the device address, word address and data bytes even when WP is asserted. No write occurs at STOP, and it is immediately ready for another command. An ACK therefore confirms bus reception, not persistence. Verify important records by readback and integrity checks.
The internal strong pulldown leaves write protection disabled. For a protected default, use a defined high level; Microchip recommends a pull-up of 10 kΩ or less. A host open-drain pull-down can then permit writes, provided reset and unpowered behavior are checked.
By Beebee Chiang | YG GROUP
The AT24C02D-SSHM-T samples its hardware WP input at STOP before starting a write cycle. Raising WP afterward does not interrupt programming. Its eight-byte page buffer has a separate roll-over rule, so reliable record storage needs both controlled write permission and correct firmware page segmentation.
An EEPROM can acknowledge every transmitted byte while still declining to program the array. That behavior matters when a host uses ACK as its only success criterion. For the AT24C02D-SSHM-T, hardware write protection is decided at the STOP condition preceding the internal programming cycle. Correct protection therefore depends on the WP level at that boundary, not merely on whether firmware eventually drives the pin high.
The exact order code is a 2-Kbit, 256-byte I2C EEPROM in an eight-lead SOIC package. The Microchip DS20006100A datasheet specifies a 1.7–3.6 V operating supply. This D revision must not inherit the 5.5 V operating claim of another EEPROM family; its absolute maximum supply is 4.1 V, which is a stress rating rather than an operating point.
Only if it fits inside the current eight-byte page. At 0x06, two bytes remain. A third byte rolls over to 0x00 in the same page. Segment the request, issue STOP, poll completion and start a new transaction for the following page.
No. DS20006100A specifies 1.7–3.6 V operation. Its 4.1 V absolute maximum supply is a stress limit and does not permit 5 V operation. Check both the supply and bus pull-up voltage against the D revision specifications.
WP high protects the full array. WP low permits writes. The pin has an internal strong pulldown, so leaving it floating enables writing; it does not establish a protected default. A defined external state is preferable to depending on that default during host reset. When pulling WP high, the manufacturer recommends a resistor of 10 kΩ or less to overcome the internal pulldown.
Table 1. Hardware write-protection conditions | Source: manufacturer documents in References; assumptions and operating conditions are stated in the table or adjacent text. Compiled / calculated by: YG GROUP.
| Condition | Specified device behavior | Host implication |
|---|---|---|
| WP high at STOP, with valid timing | Address, word address and data are ACKed; no write cycle occurs | ACK alone cannot confirm stored data |
| WP low at STOP, with valid timing | Internal self-timed write begins | Keep the supply valid until completion |
| WP changes after the initiating STOP | Does not alter or interrupt that write cycle | WP is not an emergency programming-abort input |
| Page transfer crosses an eight-byte boundary | Data rolls over within the current page | Segment writes before transmission |
The WP setup and hold times are specified around STOP. Their minimums are 4,000 ns each in standard mode, 600 ns each in fast mode, and 100 ns setup plus 400 ns hold in fast-mode plus. Do not change WP simultaneously with STOP and assume it met these requirements. Fast-mode plus operation also requires 2.5–3.6 V; the 1 MHz claim is not valid across the entire supply range.
Figure 1. Illustrative timing based on DS20006100A §7.5. WP must meet setup and hold around STOP; fast-mode minimums are 600 ns each. A later WP transition cannot interrupt an active write. Source: manufacturer documents in References; calculation / diagram: YG GROUP.
If protection blocks a write, the EEPROM is immediately available for another command instead of entering the internal write cycle. A host that only waits for an ACK can therefore mistake a protected, unchanged array for a completed write. Read back critical data or use a record-level integrity check after writes; neither a transmitted byte count nor a short polling interval establishes persistence by itself.
For a default-protected design, pull WP up to the EEPROM’s own supply and allow a suitable open-drain control to pull it low only during an authorized write window. Figure 2 shows that topology. The control must be released during reset, startup and a disallowed-write condition. Check its off-state leakage, low-level drive, voltage tolerance and behavior when its own supply is absent.
Figure 2. Illustrative WP-control circuit. DS20006100A recommends a WP pull-up of 10 kΩ or less to overcome its internal pulldown. The host must release the open-drain control when writes are disallowed; this arrangement does not protect an already-started write from supply loss. Source: manufacturer documents in References; calculation / diagram: YG GROUP.
This circuit addresses write authorization, not energy storage. A supervisor or power-good signal can prevent new writes when voltage is about to fall, but a write accepted earlier still needs valid power. Where data must survive an unexpected outage, allocate supply hold-up for the remaining programming interval and load, or use a storage architecture with explicit recovery. The datasheet specifies up to 5 ms for a write cycle. A capacitor value cannot be chosen without the real load, voltage margin, supervisor delay and regulator behavior.
The page buffer increments only the lowest three address bits. A write starting at 0x06 has space for two bytes before the boundary. Sending a third byte without STOP places it at 0x00 in the same page, rather than 0x08. WP does not repair such a transaction when writes are enabled.
For an address a, calculate page room as 8 − (a AND 7), and limit the transaction to the smaller of that room and the remaining record length. Check that the overall request remains within the 256-byte array. After STOP, use bounded ACK polling before sending the next page. A sequential read has a different rule and can traverse the array; applying write-page limits to reading is a firmware policy, not a memory requirement.
For critical settings, an illustrative recovery scheme stores two record slots, each with a version, payload and checksum. Write the inactive slot, read it back and mark it committed only after verification. On boot, select a valid committed slot. The record format and commit operation must themselves respect page boundaries. This reduces the consequences of an interrupted update but does not guarantee survival under every power-failure pattern or repair arbitrary corruption.
DS20006100A §4.5.1 requires a monotonic supply rise no faster than 0.1 V/µs. After VCC is stable at or above its minimum, wait at least 100 µs before the first command. The 1.5 V maximum POR threshold is characterized, not production-tested. If supply voltage falls below that maximum threshold, the manufacturer recommends a full power cycle with at least 1 ms at zero volts before the specified startup sequence. These reset requirements are not a promise that an interrupted nonvolatile write completed safely.
The SOIC pins are A0, A1, A2, GND, SDA, SCL, WP and VCC on pins 1 through 8 respectively. Strap address inputs to defined levels and calculate bus pull-ups from rise time and sink capability. Standby-current maximums are 0.4 µA at 1.8 V and 0.8 µA at 3.6 V under the stated input conditions; a typical-current headline is not a worst-case power budget.
Table 2. Related EEPROM comparison | Source: manufacturer documents in References; assumptions and operating conditions are stated in the table or adjacent text. Compiled / calculated by: YG GROUP.
| Model | Verified common ground | Difference to account for |
|---|---|---|
| AT24C02D-SSHM-T | Eight-lead SOIC; D-family timing and WP behavior | 256-byte array, primary device |
| AT24C01D-SSHM-T | Listed in the same datasheet and SOIC ordering table | 128-byte array; smaller capacity and corresponding word-address handling |
The related part is a capacity option, not a promise of transparent replacement. During bring-up, test a protected write and confirm that data stays unchanged despite ACKs. Then test a permitted page write, poll completion and read it back. Repeat around an eight-byte boundary, host reset and the application’s actual power transitions. A logic-analyzer capture of WP, SDA, SCL and STOP makes the protection decision reviewable; a separate supply trace determines whether the programming interval remained within operating conditions.