| Picture | Part Number | Manufacturer | Stock | Action |
|---|---|---|---|---|
 | TLC5948APWPR | Texas Instruments | 5,270 |
LED dot correction adjusts each channel's current scale with 7-bit data, making it useful for measured channel-to-channel brightness trims. Global brightness uses another 7-bit value to scale all 16 channels together. Its range is 25–100%, so BC=0 does not turn the LEDs off. Grayscale independently controls PWM on-time. These controls do not replace optical measurements or guarantee a finished display's uniformity.
LED fault readback needs correct SCLK transfers, GSCLK timing, qualifying GS latch operations and an SOUT return path. LOD and LSD results need approximately 1 µs of output on-time. At a 33 MHz GSCLK, TI specifies LATTMG settings corresponding to 33, 65 or 129 clocks, rather than 17 clocks. Check the complete write/read sequence and the selected diagnostic mode before interpreting status. Separately verify sink-voltage losses, total duty cycle and the PWP heat path; thermal flags do not validate normal operating margin.
No. The maximum-current setting reaches 60 mA only with VCC above 3.6 V; the limit is 45 mA at VCC at or below 3.6 V, with maximum DC and BC data. Continuous operation also depends on output-voltage headroom, total device dissipation, ambient conditions and the PWP thermal design. A per-channel rating does not guarantee that a particular board can operate all channels at that setting indefinitely.
By Alice Chen
TLC5948APWPR is Texas Instruments' 16-channel constant-current LED driver with dot correction, global brightness and serial fault readback. For a user-facing LED sign or display, those features can justify a more capable driver when channel matching and service diagnostics matter. This LED display driver also creates work elsewhere in the BOM: the controller must supply valid clocks and initialization data, the board needs a return path for status, and the PWP package needs a credible thermal design. Approve those resources together.
These conclusions follow the , particularly its brightness-control, register and fault-detection sections.
No. TLC5947DAPR has 24 outputs, 12-bit grayscale, an internal oscillator and a 32-pin DAP package. TLC5948APWPR has 16 outputs, 16-bit grayscale, external GSCLK, separate DC/BC controls, serial diagnostic status and a 24-pin PWP package. Compare them as different display architectures. Board connections, firmware frames, output-voltage limits and thermal design need review.
Provide the complete MPN and manufacturer, quantity, required delivery date, acceptable packaging and any lot/date-code or traceability requirements. State whether only the approved PWP ordering code is acceptable and whether engineering has approved any alternate. Ask the supplier to confirm the offer's packaging, availability, terms and supporting batch documents. A catalogue listing or an Active lifecycle label does not establish current stock or a delivery commitment.
TLC5948APWPR is the 24-pin HTSSOP PWP tape-and-reel ordering code for TLC5948A. TI lists LED video displays and LED signboards among the device's applications.
The outputs sink current from externally powered LEDs. The chip does not generate a boosted LED supply. Keep the 3.0–5.5 V logic supply separate in the design review from the LED supply and the voltage remaining at each OUT pin. TI specifies LED output operation up to 10 V; that ceiling does not mean a 10 V rail is efficient for every LED arrangement. The exact TI ordering page identifies the PWP package, −40°C to +85°C operating range and 2,000-piece large-reel carrier.
The useful procurement question is which adjustment the product actually needs. A display that only fades all its LEDs has a different requirement from one that needs channel matching, driver-to-driver balancing and service diagnostics.
| Control | What TLC5948A changes | Range and condition | Consequence for the design |
|---|---|---|---|
| Dot correction, DC | Each channel's current scale | 7 bits, 0–100% of the selected maximum, with BC also affecting current | Store and load channel trims; optical calibration still needs a measurement method |
| Global brightness, BC | All 16 current scales together | 7 bits, 25–100%; its zero code is the 25% setting | Useful for balancing driver groups; it cannot provide a complete blackout by itself |
| Grayscale, GS | Each channel's PWM on-time | 16-bit data; conventional or enhanced-spectrum PWM | Budget the grayscale clock, update timing and low-level optical behavior |
Table 1: Separate current trim, group brightness and PWM on-time. Source: TI TLC5948A Rev. A, pages 18–25, Tables 1–6. Compiled by YG GROUP.
LED dot correction can compensate for brightness deviations by adjusting individual currents. It cannot identify the required correction values without measurements, remove every optical or LED-bin difference, or restore output beyond the selected current ceiling. Reserve calibration storage and production-test time if uniformity is a product requirement.
For example, with a nominal 20 mA maximum, DC=127 and BC=0 produce about 5 mA while the output is on, before component tolerances. The same setting does not mean 25% perceived brightness: GS duty cycle, LED response and viewing conditions still matter. A blackout command should use the defined BLANK function or suitable GS data, rather than treating BC as a zero-to-full dimmer.
The controller must handle two separate timing tasks: shifting data with SCLK and generating the grayscale reference with GSCLK. Both have specified limits up to 33 MHz, but increasing one does not fix a shortage in the other. The datasheet's timing diagrams and register description show a 257-bit common shift register, a frame-select bit and separate grayscale and control latches.
Figure 1: DC and BC scale current while GS sets PWM on-time; BC=0 still selects 25% of the current scale. Useful status readback also needs a qualifying GS latch, valid diagnostic on-time and an SOUT return path. Source: TI TLC5948A Rev. A. Compiled by YG GROUP. Evidence: documentation 1.
As a calculated illustration, eight drivers require 8 × 257 = 2,056 shifted bits for one complete chain transfer. At a deliberately chosen 10 MHz SCLK, that is 205.6 µs of payload time, excluding latch operations, controller gaps and additional transfers. Control-data changes need their own correctly selected writes.
Conventional full-resolution PWM has a separate 65,536-GSCLK display period. At 33 MHz, its period is about 1.986 ms, or 503.5 periods per second before application overhead. That is a counter-period calculation, not a guaranteed image refresh rate or a camera-flicker specification. Enhanced-spectrum PWM distributes pulses within the period; TI recommends conventional PWM when using a multiplexed drive. Test the intended scan and camera conditions rather than approving the design from “16-bit” alone.
The DC, BC and GS data are not initialized to useful display values at power-up. TI defines BLANK as set and PSMODE as 111, while other control data can be random. Firmware must establish known control and grayscale data, select the intended power-save behavior and then enable the outputs. Include this sequence in the controller's startup and recovery plan.
Also check logic thresholds. The specified input-high minimum is 0.7 × VCC. With the driver at 5 V, that becomes 3.5 V, so a nominal 3.3 V controller output is not automatically guaranteed to meet it. Decide on supply alignment or level translation using both devices' electrical limits.
LED fault readback supplies electrical status for firmware to interpret. At a qualifying LAT rising edge for a GS write, status information replaces data in the common shift register after the GS data have been latched. Control writes do not perform the same status capture. Route SOUT back to the controller if the system needs to read the final device's status, and preserve the desired GS data when scheduling subsequent transfers.
Measurement timing matters as much as wiring. LOD and LSD need the output to have been on for approximately 1 µs before their result is valid. At a 33 MHz GSCLK, TI requires the later LATTMG settings—33, 65 or 129 clocks—rather than the 17-clock setting. Confirm the GS value also provides a suitable on-time, or evaluate the specified invisible detection mode.
Invisible detection uses a small selected current to check outputs even when their GS data would leave them off. It disables output-leakage detection and does not operate in power-save mode. Therefore, “all diagnostics available simultaneously under every display condition” would be an incorrect requirement.
Finally, an open-detection flag can also indicate an OUT-to-ground short. Correlate status with the commanded pattern, output voltage, supply condition and board inspection before deciding which part to replace.
The 60 mA headline requires VCC above 3.6 V. With VCC at or below 3.6 V, TI specifies a maximum-current setting up to 45 mA. Both ranges assume maximum DC and BC data; the chosen reference resistor, current-control settings and electrical tolerances still apply.
Evaluate voltage headroom across the sink at the required current, temperature and LED forward-voltage extremes. Too little headroom prevents regulation; excess headroom increases heat. As an illustrative output-stage calculation, sixteen channels at 20 mA, full duty and 1 V across each sink dissipate 0.32 W in those sinks. At 2 V, that contribution doubles to 0.64 W. Add logic-supply dissipation and use the actual pattern and duty cycle for the complete thermal estimate.
The PWP PowerPAD needs the correct land pattern, solder attachment and heat path into the PCB. The datasheet provides PWP package and assembly drawings; a similar-looking non-PowerPAD package is not the same thermal solution. Thermal warning and shutdown are protection functions, not an acceptable normal operating point. Validate junction-temperature margin and optical behavior in the intended enclosure.
TLC5947DAPR deserves comparison when the design values more outputs and an internal PWM clock, and does not require TLC5948A's current trims and serial fault data. It is a different architecture and footprint.
| Decision dimension | TLC5948APWPR | TLC5947DAPR |
|---|---|---|
| Outputs and GS data | 16 sinks, 16-bit GS | 24 sinks, 12-bit GS |
| PWM reference | External GSCLK | Internal oscillator, 4 MHz typical |
| Current setting | External resistor, per-channel DC and global BC | External resistor sets the common current; no separate DC/BC register functions |
| Specified current capability | Up to 45 mA at VCC ≤3.6 V; up to 60 mA above 3.6 V | Up to 30 mA |
| LED output-voltage ceiling | 10 V | 30 V |
| Diagnostic interface | Serial LOD, LSD, OLD, ISF, PTW and TEF status, subject to mode/timing | Thermal shutdown; no corresponding serial fault-readback register |
| Assembly identity | PWP, 24-pin HTSSOP | DAP, 32-pin HTSSOP |
Table 2: TLC5948A and TLC5947 display-architecture trade-offs. Sources: TLC5948A Rev. A, pages 1–6, 12–14 and 27–42; TLC5947 Rev. B, pages 1–8 and 12–21; exact TLC5947DAPR ordering page. Compiled by YG GROUP.
TLC5947DAPR can reduce the need for an external grayscale-clock resource, but its internal oscillator frequency is a typical value, not a precision timing reference. Its 288-bit grayscale frame and dedicated BLANK pin also differ from TLC5948A's control scheme. Changing between these parts requires board, firmware, timing and thermal review; neither the shared manufacturer nor a serial input establishes drop-in compatibility.
Choose TLC5948APWPR when the display needs its current-adjustment layers and the project will implement and validate the diagnostic path. Compare a simpler driver when those functions would remain unused. The useful approval record includes:
For sourcing, request a quotation from YG GROUP using TLC5948APWPR from Texas Instruments, the required quantity and delivery date. Include reel or cut-tape needs and any lot/date-code or traceability requirements so the offer can be checked against the approved BOM. Availability, commercial terms and supporting batch documents require confirmation for the specific offer.
